The needs of the semiconductor marketplace continue to drive density into semiconductor packages. The high end of this market appears to be standard Application-Specific Integrated Circuits (ASICs), structured ASICs, and Field-Programmable Gate Arrays (FPGAs). These devices continue to need increasing signal, power, and ground die pads. A corresponding decrease in pad pitch is required to maintain reasonable die sizes. The combination of these two needs is pushing complex semiconductor packaging designs.
Traditionally, greater wiring densities are achieved by reducing the dimensions of vias, lines, and spaces, increasing the number of wiring layers, and utilizing blind and buried vias. However, each of these approaches possesses inherent limitations, for example those related to drilling and plating of high aspect ratio vias, reduced conductance of narrow circuit lines, and increased cost of fabrication related to additional wiring layers. One method of extending wiring density beyond the limits imposed by these approaches is a strategy that allows for metal-to-metal z-axis interconnection of sub-composites during lamination to form a composite structure.
Conductive joints can be formed during lamination using an electrically conductive adhesive. As a result, one is able to fabricate structures with vertically terminated vias of arbitrary depth. Replacement of conventional plated through holes with vertically-terminated vias opens up additional wiring channels on layers above and below the terminated vias and eliminates via stubs which cause reflective signal loss. More and more substrate designs require signal paths that can handle frequencies on the order of multi-gigahertz.
The challenges for organic substrates in meeting these electrical requirements include using high-speed, low-loss materials, manufacturing precise structures, and making a reliable finished product. In addition, many high-speed chip packages have mechanical and environmental requirements such as light weight and low moisture absorption. One material that meets all of these requirements is a liquid crystal polymer (LCP) dielectric that has a unique combination of features and performance. Due to its design flexibility, lighter weight and especially hermeticity, LCP-based Z-interconnect has potential to be a favorable alternative to low temperature co-fired ceramic (LTCC) substrates. In addition, the lower dielectric constant of LCPs can reduce crosstalk and noise coupling compared to LTCC substrates.
Electronic substrates require hermetic or near hermetic seals to reduce loss and to protect circuits in harsh environments. Any water that is absorbed by substrates increases the signal loss in that substrate, especially at GHz frequencies. Also, any circuit in an environment with much water or dust or dirt, should be sealed from these outside debris in order to continue functioning.
Currently, most hermetic seals are using machined metal enclosures. Using LCPs to seal a substrate results in orders of magnitude lighter weight and less expense than metal enclosures. In addition, LCP material can be part of the processing of the electronics, rather than an additional assembly step. This reduces the cost and complexity of assembly even further.